0:03 hi everyone welcome to vlsi academy this
0:05 is a continuation lecture on sanity
0:08 checks related to the floor plan which
0:11 must be performed to ensure the smooth
0:13 execution of your steps related to
0:15 physical design so without any delay let
0:17 us get started in previous lecture we
0:20 broadly covered what sanity is xr so
0:22 there were net list related checks there
0:25 was sdc related checks and linking
0:28 related checks and netlist versus sdc we
0:30 had covered why we should be doing the
0:32 sanity checks why it is important and we
0:35 also covered in detail what netlist
0:38 related checks are so uh out of those
0:41 netlist related checks there were first
0:45 was output should not output should be
0:47 should not be tied to the ground so
0:49 output should not be
0:52 tied to the ground that was the first
0:54 check that we saw in the net list
0:56 related checks and then second check
0:58 that we saw was
1:00 input should not be floating so there
1:04 should not be any floating input no
1:06 floating inputs in the design are
1:08 allowed we have seen that in detail why
1:11 it is important then we also saw that
1:14 there should not be any multi-driven
1:16 nets so there should not be any
1:18 multi-driven nets in the design that
1:21 also we covered in detail then last we
1:24 saw was there should not be any
1:27 combinational feedback loops so there
1:29 should not be any combinational feedback
1:32 loops or you can say that no timing
1:34 loops should be present in the design
1:36 this combinational feedback loop creates
1:39 a problem in the sd also and hence it
1:42 should be avoided so we have seen all
1:45 this and now we will cover in detail
1:47 what are sdc related checks let us
1:50 assume this is our design and there are
1:53 certain ports at the bottom these are
1:56 your interface ports and hence in our
1:59 sdc related checks first expectation is
2:02 your i o delay must be properly defined
2:05 if your i o delays are not properly
2:08 defined then the interface timing will
2:10 not be correct we have covered the
2:12 contents of sdc in one of the previous
2:15 videos you can go and watch that video
2:17 so in that input delay and output delay
2:20 are specified using set
2:24 underscore input underscore delay this
2:26 is for input related and
2:30 command for output is set underscore
2:34 output underscore delay we have covered
2:36 that in detail how do we specify all the
2:39 constraints so first expectation is your
2:41 io delay should be proper for the proper
2:44 interface timing the second sdc related
2:47 check is there should not be any
2:50 unconstrained endpoints so if you have
2:54 any unconstrained endpoints that means
2:56 you have a timing path but it is not
2:58 constrained if the constraints are
3:00 missing that means your sdc is not
3:02 correct so unconstrained end point
3:05 should be zero we will not be able to
3:07 perform timing analysis and optimize
3:09 properly if you have unconstrained
3:11 endpoints in the design the third check
3:14 is related to the flip flop clock pins
3:16 so if let us say this is your flip flop
3:20 and this is your clock pin so there
3:22 should be a clock should be reaching to
3:25 that clock pin so we have to check for
3:26 that that
3:29 no if there is no clock
3:32 reaching to that clock pin then timing
3:34 optimization will not be correct so no
3:37 clock reaching to the
3:38 flip flop
3:39 clock pin
3:41 if that is the case then timing
3:43 optimization will not be correct and
3:45 setup and hold checks will not be
3:48 performed on this particular data pin of
3:51 this flip flop so that is not a correct
3:54 expectation and hence that could happen
3:56 probably because there is no clock
3:58 attribute set on this particular clock
4:01 pin or even if it is set it might be
4:03 propagate not propagated properly or
4:05 there could be some other constraint
4:07 missing on the clock pin so
4:09 because of this that could happen so we
4:12 need to check for this also sometimes
4:14 what happens is let us say that this
4:18 macro is a macro and its pin is this pin here
4:18 here
4:21 and this pin is getting clock from this
4:23 clock source which is giving the clock
4:27 as clk a and there is also clock coming
4:29 from the different clock source which is
4:31 clk b
4:34 so what happens is you are getting
4:37 multiple clocks on a single clock pin it
4:40 could be either macro or it could be on
4:44 a standard cell also so both we have to
4:45 check for standard cell and macro all
4:48 the clock pins there should not be
4:50 multiple clocks driving a single clock
4:52 pin so it is similar to
4:54 no multi driven nets we have seen that
4:57 in earlier case of sanity checks so no
4:59 multi driven net should be there it is
5:03 specifically for clock nets so no multi
5:05 driven clock nets there is an
5:08 exception that if you have multi-source
5:11 cts which is a specific cts that we will
5:13 discuss later on in that case you can have
5:14 have
5:16 multi-driven nets but that is an
5:18 exception and a special case we have
5:21 seen in previous videos that cell delay
5:25 is a function of input transition and
5:27 output load we have seen that already
5:30 and this transition is of input pin and
5:34 output load is on output pin so for for
5:36 defining every cell delay it is
5:39 important and while defining for a port
5:43 also it is needed so if you do not have
5:45 any input transition defined for a
5:48 particular port that is also a problem
5:51 hence while defining a port also so let
5:54 us say that this is one port this port
5:57 is connected to some cell inside and
6:00 then let's say this is an input port so
6:03 the connection will be like this inside
6:05 now we need to define something which is
6:08 connecting outside otherwise this delay
6:11 will not be properly modeled and hence
6:13 we should define something like set
6:16 input transition so let us say that for
6:19 all transitions for all the ports if you
6:21 want to define as
6:23 together so you can define like this set
6:26 input underscore transition
6:28 so set input transition is the command
6:30 that you can use to define some
6:33 transition let's say 200 ps and if you
6:35 have the values in ns
6:37 and inside this you will give all the
6:39 input ports so that will be all
6:41 underscore inputs
6:43 that way you can define so set
6:45 underscore input transition is the
6:48 command to use used to define the
6:51 input transition of the all input ports
6:53 similarly for defining proper
6:55 constraints for the output ports we must have
6:56 have
6:59 a defined load on the output ports if
7:01 you do not have defined then you can
7:05 define like this set underscore load and
7:08 let's say some 25 peak of error you want
7:10 to define the load as capacitance and
7:13 here you will give all underscore outputs
7:14 outputs
7:16 so this is the command you can use to
7:18 define the load and the output ports so
7:21 the requirement becomes
7:23 that you should have input transition
7:25 transition and
7:26 and
7:27 output load defined
7:29 defined on
7:31 on
7:34 all inputs and output ports on all
7:36 input and
7:39 output ports this is a requirement to be
7:41 defined in the sdc that is all for this
7:43 video we will come up with more concepts
7:46 in further videos please do like share
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