This lecture details the initial stages of RTL (Register Transfer Level) synthesis, focusing on parsing and elaboration, and explains how Verilog constructs are translated into hardware logic gates.
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everybody Welcome to the course vlsi
design flow RTL to GDs this is the 12th
lecture in this lecture we will be going
in the earlier lectures we had seen that
the logic synthesis consists of various
smaller tasks for example the RTL
synthesis then logic optimization then
technology mapping and then technology
dependent optimization
so the first part of logic synthesis is
RTL synthesis and in RTL synthesis what
do we do so we basically translate we
translate the given verilog code or the
RTL model into a net list consisting of
generic logic gates so this is the this
is the the responsibility of RTL synthesis
synthesis
so the RTL synthesis is also a
complicated task and we further break it
down into smaller tasks so the smaller
tasks are parsing elaboration and then
translation of various very low
constructs in the code to the uh to the
logic gates and also some optimizations
which are RTL construct specific
so in in this lecture we will be looking
into the parsing and elaboration and the
translation of some of the important
very lock constructs and in the next
lecture will be uh going through uh the
translation of more very low construct
and also look into the optimization
so the given an RTL code or an art very
log model
um representing an RTL the first task
that is done by the by the RTL synthesis
tool is to read the given RTL file files
and populate a data structure for
further process
so ah in the earlier lectures we had
seen that the verilog code consists of
various uh it consists of uh characters
and characters can be grouped together
into tokens and we have various types of
tokens for example identifiers keywords
operators and so on right so the given
an RTL file and a very low code so the
first task that is done by the by the
tool is
known as lexical analysis so the lexical
analysis basically ah breaks down the
given RTL code into tokens various kinds
of tokens for example keywords
identifiers and so on
and after this lexical analysis it
checks for the grammar of the of the of
the of the given code whether it it is
following the ah the prescribed
syntax and syntax of the verilog
language and if there are say errors
then the the in the in that case the uh
the tool will report report syntax error
in the code
if the given code doesn't doesn't follow
the the the grammar of the verilog language
language
ah but if the if if the given RTL code
is uh is a syntax error free meaning
that it is following the grammar
correctly then what the tool will do is
that it will build and build an uh data
structure which is uh typically a kind
of syntax tree or a parse tree and this
is a kind of hierarchical data structure
so by hierarchical data structure we
mean that ah the if some object RTL
construct is contains some other RTL
construct then the apparent child
relationship is maintained and so on so
that makes a kind of an a hierarchical
data structure or that based on the
parent child relationship a hierarchical
data structure is built for the given uh
very lock code so let us take an example
that how it is done so suppose we we are
given uh or the tool is the RTL
synthesis tool is given a verilog file
in which there is a module say top okay
and for Simplicity we are not showing
the internals of this top module and
there is another module say made
and it contains an always block and so
on now for this code what will be the
the the syntax tree or how will that
syntax tree look like
so it will be something like this so
there will be at the top there is a root right
right
and so so verilog is in very long the
module is the top most comp entity of a
design so there will be if the root will
have as children various modules so in
this case there are two modules top and
mid so those will become the children of
the root and then the in in mid we have
the in the in the given code uh we have
an always block so always block is
contained within mid so the always block
will be a child of the module mid right
and then within ah always block there
are three statements right we have three
statements so each statement will form
one child right so there are two
non-blocking statements non blocking
statements right these two are non
blocking statements and those will
become a non-blocking state
so two child will be created uh
corresponding to those non blocking
statement and one child will be created
uh corresponding to the blocking
statement right now each statement has
an LHS and rhs right so the the this
non-blocking statement will contain LHS
part and the r just part and so on so
this is how the the the the the given uh
verilog code will be will be passed and
a data structure will be built a
hierarchical data structure and then
once this hierarchical data structure or
pass 3 is built then the the RTL
synthesis goes synthesis tool goes to
the next step and what is the next step
the next step is called elaboration so
what is done in elaboration so in
elaboration the RTL synthesis tool
checks whether the connection among the
RTL specific components are legitimate
right so
um we will understand what do we mean by legitimate
legitimate
connections OK and if it is legitimate
legitimate then the then the during
elaboration the connections are made in
the internal model that is the the that
is used to represent the given very log
code okay so let's take an example
Suppose there was a that there was a
design in which we have say one module
Leaf right we had this is a leaf level
module and then there is another module
middle right there is a module medal
which contains an instance of leaf right
so this is an instance instantiation of
leaf so the leaf we say that for this
instance F1 F1 is the name of the
instance the master module is
is a leaf because the name here is
referring to this other module so the
master module of this instance F1 is
leaf and then there is another module
say top and inside top we have three
instances two instances of leaf right so
i1 and I2 are the is are the instances
with master module as leaf and I3 is an
instance whose master module is mid this
one right so this is this is the given
RTL code if we give this code to the RTL
synthesis Tool uh then during
elaboration the linkages between the
leaf level module sorry the the
instances and the master modules are
made and in this instantiation if there
are some problems of connections then
those connect problems are reported and
as elaboration error for example if we
say that the master module is leaf and
in leaf we have three ports D clock and
Q right and here we have written D clock
and Q so here that there is no problem
but suppose we made an error and instead
of writing D here we wrote here D1 right
so the this kind of error will be create
there will be
reported by the RTL synthesis tool
during elaboration so when the when the
when the initially the RTL code is read
at that time there is no no linkage is
created between the instances and their
master module right so those in during
the initial stages the code is read
module by module so at that time the
tool doesn't know that what is the
direction of the input this pen D clock
and Q and so on right so the tool can
actually make uh may make some
simplistic assumption initially so for
the for the leaf level module Leaf level
level module Leaf the tool can
understand that the direction of input
pin is d
input pin D A or sorry the the direction
of Port D is input it will be creating
for the clock it is input for Q it is
output right but when it will create the
module middle
it will take an is it will uh it will
process the instance F1 right so it will
create an instance F1 but while
processing this module while processing
this module the the tool will before
establishing the linkages between the
instance and the master module it
doesn't know that what is the direction
of this pin D this pin clock and this
pin Q so the tool can make some
simplistic assumption like treating all
of them as input pair right so
um similarly in the module top there are
three instances Lee or two of leaf and
one of mid right so in at when the Tool
is is analyzing this particular module
top at that time it doesn't know that
what are the directions of these pins
pins D clock q and so on and it can make
and simplestic assumption that all all
pins are input pins right and after
elaboration what will it will do is that
it will create linkages between this
this instance and the master module this
instance and the master module and this
instance in the master module and then a
design hierarchy will be built and the
connections will be also be created
so let us understand that after
elaboration What will what will happen
so this was the the the the the view of
the design when when no elaboration was
done so in this case what we see that
the modules are separate so the modules
and instances are totally separate but
after elaboration those will be linked
together so now at the top level so this
is the top level module in this top
level module we have two instances
of leaf with name i1 and I2 and now the
directions of the
pins are inferred from looking into this
ah master module of leaf and D will the
direction of
pin D will be taken as input for pin
clock it will be taken as input and for
the PIN
Q it will be taken as output similarly
the the correct direction will be
inferred and then and are linked a
design hierarchy will be built and also
the connections will be made right now
during this stage there can be errors or
elaboration errors that the tool can
report now when can the error be so
there are some common situations suppose
while we are while we are running the
logic synthesis tool or RTL synthesis
tool and we we get and these three
modules these three modules were in
separate verilog five and by mistake we
gave only these two files and forgot to
give this 5 right in that case the tool
will not be able to establish that what
does this module Leaf is right because
the master module of the the master
module of the instance F1 is leaf and we
have not given the module corresponding
to leave by mistake right so if we make
such kind of mistake then the tool will
not be able to establish the linkages
between the instances and the master
module and as a result what it will
happen is that it will the tool May
report an error it will report an error
that there is no reference of module
Leaf in the RTL files and therefore it
is assuming leave to be a black box
right now this is a situation which is
which which we encounter commonly in in
in in our in logic synthesis and it
means that probably the we have not
given the reference of or we have not
given the the given the module which
contains the description of the module
leave right so that is one mistake that
can be made or that can be reported
during elaboration that the black boxes
in our ah in in our design right so
typically there shouldn't be a black box
in our design otherwise even the
direction of the of those pins will not
cannot be inferred for its their
instantiation and then the the tool can
behave uh unexpectedly so we should look
into the the the the warnings or errors
corresponding to Black Box in our design
carefully then other kind of Errors can
be with respect to the port names for
example if we make error in the name of
the ports while instantiating then in
that case the that problem will be
reported during elaboration or there is a
a
mismatch in the width of the of the
buses and the pins in the instantiation
then the tool can report error okay
another responsibility of elaboration is
that it it processes parameterized
module so in earlier lectures we we
discussed that verilog supports
parameterized modules meaning that we
can have parameters in our module and
based on the value of the parameter the
module can have different interfaces for
example the the width of a bus or a port
can change based on the parameter and
the parameters value can be different in
different instances so in that case what
the tool enter will do the RTL synthesis
tool will typically do the it will
create separate modules with different
interfaces for each distinct set of
parameters okay now what it means let us
look into an example and then we'll understand
understand
so Suppose there was a parameterized
module counter with a parameter width
with a default value of 4 right and the
there are in there is an output Port
output port with the name count and its
uh its size depends on the value of this
parameter width right so the the the
if the value is default value then the
out the the output Port count will be
three down to zero right it will be 4
bit wide right now during instantiation
we can change the value of the of the
parameters for example in in this
instance C1 we are not changing so in
this case the default value of 4 will be
used for count 3 right first the
instance C1 for the another instance C
two we are saying that instead of 4 use
a value of width as eight so in this
case the value the width of the bus so
width of the port count will be 8
instead of 4 right and similarly in the
third instance in the for the c three we
have want the width to be 60 right now
in this case what the tool will do it
will internally create three different
modules one for with four another for
width a eight and third one for weight
sixty so how will the our design look
like it will look like something like
this so for the for the instance C1 with
the the count will take a value of 3 2 3
down to 0 or it will take a width of 4
for C two eight and for c three it will
be taking sixteen right now what will be
the name of this this new modules that
will be created during elaboration so it
is tool specific typically it will use a
combination of the name of the parameter
and its value so it may be say count the
master module name initially was a
counter so in this case after during
elaboration the new module will be
created and its name can be counter
underscore width underscore 4 for the
for the for this module for the other it
can be counter underscore width
underscore 8 tools denote that the value
of the width is 8 and so but note that
this name is ah the the name of the um
the master module that will be created
by the tool it is tool specific the tool
is free to choose any name
before going through ah various RTL
constructs and understanding how they
are synthesized to logic gates first let
us understand that which RTL constructs
are or verilog constructs are
synthesizable and which all are not
synthesis synthesizable why because some
verilog constructs are there which
support other other design tasks such as
functional verification and those are
not meant to be synthesized right so a
given RTL synthesis tool may not support
all synthesizable verilog constructs
right this is also a point that should
be noted that there is no the the
language as such doesn't say that what
is synthesizable and what is not
synthesizable right so the tool tool it
it is very much tool specific that which
which RTL construct uh uh is supported
by that tool for synthesis and which is
which are which which is which
constructs are not supported by the tool
and therefore as a designer we should be
aware of the verilog constructs which
are supported by the synthesis tool that
we are using and then and then write out
verilog code and so on in in taking that
into account so there are some RTL
constructs which are typically not ah
not uh not supported by RTL synthesis
tool so let us understand strand or take
a look at them so the first thing we
should note is that the delay specification
specification
for example if we write a statement out one
one
which is assigned to a after delay of
say 12 time units
so this kind of delay specifications are
not supported by synthesis so these
delay specifications are typically
useful for simulations right in the
simulations we want to understand that
we the very low code or we want to
um verify that whether our RTL model uh
behaves correctly
when there is a delay of say 12 time
units right so the hash has delay kind
of constructs if it exists in the RTL
code it should be interpreted as that
this means this this delay is meant to
simulate and see that what happens to
our RTL model if this much delay happens
right but it is not meant to uh say to
the synthesis tool that insert a delay
element which has a value of 12 time
units right so the delay is typically
what the the synthesis tool will do is
that in these cases the delays delay
delay specification for example uh the
has 12 in this case will be totally
ignored so the RTL synthesis tool will
treat the statement as out one is
assigned to a in a non-blocking manner
that's it right so the hash 12 will be
totally ignored
okay so ah there are other RTL
constructs which are are not supported
in synthesis for example initial blocks
or initial blocks are useful in writing
test benches that we have seen earlier
right and then there are four Joint
Force release and uh data types real and
time these are not supported for
synthesis and there are system tasks for
example dollar display dollar Monitor
and others those are not supported by
the synth RTL synthesis too so these are
these these system tasks are useful in
verifying our design or or doing
functional verification or simulation
now let us look into the RTL constructs
which which are synthesizable and how
they will be synthesized so first let us
look into the assign statement right so
the continuous assignment statement so
how how is a continuous assigned ah
continuous assignment or assign
statement synthesized if it exists in
the RTL code so corresponding to the
assigned statement a combinational
circuit will be inferred and what
combinational circuit will be inferred
it will depend on what is on the rhs of
the assigned statement so let us take an
example and understand this suppose we
are there is a module top and in which
we have say three assigned statements so
the first assigned statement says out 1
is equal to a and b or c right so this
is the rhs of of the assigned statement
and the logic will the or the or the the
synth RTL synthesis tool will
instantiate logic gates corresponding to
the ah rhs so it will be something like
this so for the output Port out one
right it will be us
an and and an or gate will be
instantiated corresponding to these
operators these logical operators
similarly for out two since out 2 is of
a size 4 right it is a it is a bus of
size 4 so in this case and X and Y are
also of size 4 so when we assign out 2 2
is equal to X and Y there will be there
will be four ah and Gates that will be
instantiated right so x 0 y 0 will be
added and out to 0 will be driven by
that and so on and for the third one out
three we have a ternary operator so when
s is true then Q the Out 3 takes the
value Q otherwise it takes a value of P
so this is a description corresponding
to a multiplexer so the tool will ah
will instantiate a multiplexer in which
s is s is appearing on the condition
right so the S will be on the select
line and P and Q will be on the data line
now let us look into how the statement
if else will be synthesized by the RTL
synthesis 2. now if else is a kind of a
multiplexer kind of thing meaning that
if something happens then the then one
line will be selected otherwise some
other line will be selected so
corresponding to if else statement uh uh uh
uh
multiplexer will be instantiated in our
design and the select line of the
multiplexer will be there will be
corresponding to the condition that
appears in the if if condition right so
let us take an example and understand so
let us say let's let's look into this
always block right in this always always
block there is an if else statement now
if s is equal to 0 right s is equal to
one tick P0 that is s is equal to 0 then
out 1 is equal to
a right if s is 0 then out 1 is equal to
a else out 1 is equal to B so
corresponding to this a multiplexer will
be created right so out one will be
driven by this multiplexer on the select
line will have s y will have S because
it is coming in the if condition right
so here we have the select line and when
a select line takes a value of 0 then a
is driven to the out one port right and
as described as as represented in this
RTL code and if out one if if s takes a
value of 1 then B will be driven through
the or to the output Port right so this
is with the how the how the an if else
kind of RTL construct will be
synthesized by the RTL synthesis 2.
now how will the case statement be
synthesized so the case statement will
also be synthesized into a multiplexer
or a select logic select logic is
inferred so the size of this multiplexer
will depend on what is the what is the
complexity of the case or the or the or
the signal appearing in the in the case
statement which is selecting various
values right for example in the suppose
we have a state case statement like this
case statement is like this so in this
case statement we have the ah the
selection is based on the signal s and
what is the size of s the size of s is
of two bits so in the multiplexer that
will have will have two lines on the two
bits on the select line right so this
kind of case statement will basically ah
translate into into a four to one
multiplexer because there are two select
lines as 0 and S1 right
and if if these two take a value of 0 0
right then line a will be selected right
if they take value of 0 and
sorry this one is one and this one is 0
then B will be selected and so on right
so this is how the case statement will
be selected right now in a case
statement verilog supports that there
can be multiple matches right so if if
we write say question mark or don't care
conditions in that case there can be
multiple matches and in that case what
will the behavior of the verilog code it
will be that whatever matches first that
will be selected by the case statement
right that is what is defined by the
language and therefore if there are
multiple matches in the case statement
then the tool will uh will infer or
instantiate a kind of priority logic
right so let us take an example and and
understand it now suppose this we the
code is like this the case statement is
like this right now s is again of 2 bit
means it is a two bit line right now how
many possibilities are there for this
this signal to take right so it can take
zero zero zero one one zero and one
so what we are saying is that if in or
what this description says that if one
question mark means that this can take
any value 0 or 1 out 1 takes a value of
a right meaning that if it is 1 1 or 1 0
in both these cases a value of a will be
driven to the output right and then
what's the what the second line says
that if if it matches either with 0 1 or
1 1 it should it should out one should
be driven to B but note that the case 1
1 is already covered in the first case
right so it cannot match in the second
case right so only zero zero one case
will take take a value of B and then
default is d 0 0 and in the 0 0 case out
one will get a value of C
right so now we have to instantiate
logic gates such that this kind of
priority is maintained in the logic
structure or the or the or in the
implementation of the circuit so let us
look into how the instantiation will be
done so it will be something like this
so if what we have we have here is that
if S1 takes a value of 1 right if k s 1
takes a value of 1 then out 1 gets a
value of a right it will get the value
of a this line will be totally ignored
right so what it means is that if the Y
if the the value of s is 1 0 or 1 1 in
both cases out one will get a value of a
so this is what we wanted our priority
to be right now if it it does not match
the the it it does not get the first or
it does not match the first statement or
first condition one question mark then
it goes to the next statement and in
that next statement what it does is that
it looks for S 1 in the S 0 or the lower
bit right so if s 0 bit is one then B
will be selected and it will be going to
out one and if s 0 is 0 then C will be
selected and to the output so the
required priority that we wanted to have
in in as described in this RTL code that
is maintained by this circuit right
so this kind of priority can also be
enforced by if else if kind of construct
in that case case also the ah a priority
based logic gate structure will be
implemented in the ah in the in the in
the net list generated by the RTL
synthesis 2.
now let let us take a few examples of
the often always block and then
understand that how always block will be
synthesized so first let us take a next
a few examples for the case when the
always block is Edge sensitive right so
ah let us consider this module D flip
flop so in this module we have an always
Block in which which is sensitive to the
clock signal clock and whenever a
positive Edge to the clock signal
appears then whatever in there on the D
that appears on the Queue or that is
assigned to Q otherwise Q retains its
old value so this is a description of a
d type flip flop and for this in this
module will the RTL synthesis tool will
basically instantiate a d flip flop as
as shown here right so whenever a clock
positive Edge appears set the clock
whatever is in the data that will be
propagated to the to the Q pin and it
will appear at the Port queue
now let us take another example in which
the always block is sensitive to both
clock signal and the reset signal right
and it is sensitive to possessed clock
and negative reset so when reset takes a
value of 0 then Q is assigned a value of
0 otherwise Q is assigned a value of d
right so note in this case that this
clock and reset these two signals can
appear or ah independent of each other
right and therefore this is this is a
kind of this reset signal is a kind of
an asynchronous reset meaning that it
can come anywhere during any time or of
the clock period and the it can reset
the reset the ah the the flip flop right
so corresponding to this description uh
flip flop will be instantiated in which
there will be an asynchronous reset pen
asynchronous reset pin and there it is
it will be it is sensitive to or reset
is active when it takes a value 0 and
therefore will have a bubble here
meaning that when reset is equal to 0
then Q will take a value of 0 right
now let us take another example of an
always block which is sensitive just to
the clock signal so the Val this always
block will be triggered only when poses
clock appears right now but when it
enters it looks for first the signal
reset and if reset is equal to 0 then Q
becomes 0 right otherwise Q takes a
value of T right so once the clock Edge
comes then it looks whether that deep in
sorry the what is the value of reset if
reset is equal to 0 then Q becomes 0
right so it is a kind of a synchronous
reset kind of thing right so we can all
look under look into this part and
consider it as a multiplexer right and
therefore circuits like this will can be
can be inferred by the two right so
there is a flip flop right this flip
flop and the D input that is coming to
the flip flop it is either 0 or D
because this if struct if if else
statement corresponds to a multiplexer
that we have seen earlier right so if
reset is equal to 0 reset is equal to 0
then this line will be selected on one
and in the on this line will have a
zero constant value assigned to this
multiplexer and then if the reset value
is 1
then whatever is D that appears on the
or the D Port that appears at the D pin
of the flip flop right so now this is
how this ah how this module or this RTL
construct will be synthesized right now
the tool RTL synthesis tool can further
optimize it for example instead of using
a multiplexer it can use an and gate or
so on right so whatever we are
discussing in this lecture the tool May
instantiate some other logic gates also
right so you you should note this point
that what we are showing in this Slide
the tool May instantiate some other
logic gates also but whatever the tool
will instantiate it will be functionally
equivalent to what we are discussing in
this or showing in this slide so instead
of say multiplexer the tool can always
instantiate and add an or gate and then
and so the exact implementation of the
RTL construct is dependent on the tool
right so for a given Boolean function
tool can implement it in many different
kind of ways but the uh the the meaning
of based on the meaning of the of the
verilog construct
some the tool will always generates ah
generate a circuit which is functionally
equivalent to what we are discussing in
now the always block can be synthesized
in different ways depending on whether
we are assigning a signal in a blocking
manner or non-blocking manner okay so
let us take an example and understand it
so the another important point that
should be noted is that the verilog
language as such was invented for the
primary purpose of simulation or
verification right so very log you might
remember that verification a very long
language or the word verilog was derived
from verification and logic right so the
initial purpose why verilog was invented
was for verification using simulation so
the syntax and semantics of simulation
was very well defined initially and then
later on the verilog language was used
for the synthesis for logic synthesis
RTL synthesis purpose so later on when
RTL synthesis tools were developed
they use the same sim syntax and Sim or
ah they followed the semantics of the of
the simulation that was being followed
in the synthesis also right so the
handling of blocking and non-blocking
assignment in always block is done
differently how it is done it is done in
the manner such that it is consistent
with the simulation right that is what
the what is an important point to note
so once we understand that what is the
how things will be simulated then the
synthesis tries to mimic that thing
right so let us take an example and
understand it
so suppose this there is a all there is
there is an always Block in which there
is a clock signal it is so this always
block is triggered by uh whenever pauses
appears at the clock signal so whenever
now in this always block all the all the
assignments are in a blocking manner
right so it is similar to a programming
language the first statement will be
executed then the second then third and
fourth in sequence and the all the
statements will be execute when one
statement is executed the other I others
are blocked and so on right so in this
case whenever the clock signal poses
clock appears then whatever is it at N1
that will be assigned to region and then
whatever is in at Ridge one
that assigns get assigned to rest 2 and
then whatever is at rest to that assign
2 gets assigned to rest 3 and whatever
is at rest 3 that gets assigned to out
one right so all this assignment happen
at a single clock Edge right so in
effect whenever the clock Edge poses
clock as appears whatever was at N1 that
appears at outward right so in effect
this res 1 rest 2 rest 3 these are
redundant right these are not nor so in
effect what is what this always block is
doing whatever is at N1 that is passed
to out one in whenever the clock Edge
appears right because the all these
statements are executed in sequence and
as a result finally what happens that
out one gets a value of N1 so in this
case the tool will instantiate only one
flip flop and the the D pin will be
connected to in one and the Q pin will
be connected to Output right so this is
how the tool will synthesize this always block
block
now let us take another example now in
this example the everything is same only
thing difference is that we are using
non-blocking assignment right now
remember from earlier discussion that
the non-blocking assignment is executed
in a in two steps in the first step
whatever is the a is on the rhs that is
evaluated and scheduled to be assigned
to the LHS later on at the end of the
simulation right so what happens in this
case whenever clock Edge appears
positive a clock Edge appears so
whatever was that value of current value
of N1 that is assigned to reg1 right is
sorry that means not assigned to Regis 1
but that is scheduled to be assigned to
Regional right that is an important
point the value of reg1 is still the old
value but the what the regiment value
will be assigned later on it is the
value of in one right and then in the
what happens to the rest to the current
value of Regis 1 it is not yet updated
to in one right so whatever is the
current value of Rich one that is
scheduled to be assigned to rest 2 but
rest to value is still not updated right
and in The Next Step whatever is the
current value of raised to that is
assigned to raise three and the rest 3
value is not yet updated and the in the
third case whatever is the value of of
current value of rest 3 that will be
assigned to out one but is ah but out
one is not yet updated now when at the
end of the simulation all these updates
happen so in effect what happens is that
the the the the the current value of
region so the it will the this this kind
of structure will be synthesized to us
shift register kind of thing so this
will be this register will correspond to region
region
this register will correspond to
reg 2 this one will correspond to rest 3
and this one will cause for 2 out 1
right so four registers will be ah will
be will be ah will be created in this
case and the and the whatever the value
of N1 is that will be assigned to Reg 1
right but it will be assigned when the
clock Edge comes right and what was the
current value of region that will be
assigned to raise two and so on right so
this is how it will be synthesized now
let us look at the when an always block
is level sensitive then how it is synthesized
synthesized
so when always block does not contain
edges in the sensitivity list then
either combinational circuit elements or
latches will be inferred and when the
value of the variable is updated in
every com possible paths in the
conditional branches within an always
block then combinational circuit
elements will be ah will be will be
inferred and if there is some path if
the variable is in there is some path in
the conditional branches where the
variable retains its old value then a
latch will be inverted right so let us
take an example and understand what it means
means
so let's consider this module top in
which there are two always block
in the first always block we see that
out one variable is assigned a value of
a when s takes a value 0 and assigned a
value B when s takes a value 1. so s can
take either 0 value or one value and in
both cases either 0 or 1 sorry either A
or B is being assigned to out one so out
one is assigned in all conditional
branches within the out within the
always block and therefore in this case
combinational circuit element and
specifically a multiplexer will be
inferred now let us look into the other
always block now in the other always
block if
the enable signal is taking a value of 1
then out 2 takes the value of C right
and if it is 0 then what happens
it is not specified right so in that
case if enable takes a value of 0 then
out 2 retains its old value because then
it is not not ah or the value of out 2
is not being refreshed or being written
in that case when enable is equal to
zero so it means that whenever in this
block this always block is is triggered
and the value of the enable signal is 1
then out 2 will re sorry whenever the
value of the enable signal is 1 then out
2 will get a value of C otherwise it
will retain its old value right so we
can consider this always block and the
one shown here as equivalent right so
when we write if enable is equal to one
tick B1 then out 2 takes a value of C
else out 2 is equal to out 2 it is
retaining its value right and if we
write a if we draw a circuit for this
again it is an if else kind of structure
and therefore a multiplex plexor will be
inferred it will the multiplexer will
look like something like this right so
whenever enable is 1
right whatever is at the deep end sorry
at the C line that will go to out
otherwise it will take the old value and
therefore we have made a connection of
feedback right now this lag sorry the
multiplexer with the feedback is similar
to a latch right so this structure this
complete structure is nothing but a
latch right a delatch remember that what
is a d latch
so if a deal if you a d latch just to
recap what is a d latch in D latch has a
pin as D and enable and a third penis
queue so whenever enable is high
whatever is the value at D that goes to
q and whenever the enable is zero then
it holds the previous value right so in
this and this this the description that
shows shown in this figure is the same
if enable is equal to
ah is equal to one then whatever is C
that appears at out two otherwise it
retains the old value there is a
feedback right so corresponding to this
module top the two two ah instances will
be created first for with resp for the
all always Block in which out one is
being written in all conditional
branches and therefore a multiplexer or
a or a or a combinational circuit
element will be in purely combinational
circuit element will be ah inferred and
for the second always block a d latch
so ah sometimes we actually want the
latch to be or latch to be inferred
because of the always block but many a
times at what happens is that latches
get inferred because of wrong coding RTL
code coding
what happens is that lot latches often
get inferred due to incurrent incorrect
modeling of the combinational block and
what what mistake we can make we can
inadvertently Miss updating values in
one of the branches of the case
statement suppose we are writing a code
for an FSM or a stay or or some RTL code
in which there is a complicated case
statement right so a case statement in
which the select line is say of eight
bits and based on the value of of the
select line various operations are being
done right and in we wanted this case
statement or case block to be inferred
to a purely combinational circuit
element but because we missed some of
the case statement a latch will be
inferred because whenever for the cases
where we have missed the assigning value
to the uh to a variable it implies that
it will retain the old value and
therefore a latch will be a infer right
for example consider this code in this
code we have in one is the is on the
select line for the for the case
statement now it has got two bits right
so there are four possibilities zero
zero zero one one zero and one one for
the signal in one right now for 0 0 we
are writing the value of out one for
zero one we are writing the value of out
one and for one zero we are writing a
value of out one but for the case one
one we have missed writing a value right
that may be a mistake and an inadvertent
mistake while writing the RTL code and
therefore in this case a latch will get
inverted So to avoid such problems what
we can do is that we use default
statement so whenever there are
complicated cases at the end we also a
case statement at the end of the case
statement we also write default and for
example and then we write write out 1 is
equal to say one take B zero so if we
use a default statement then
for the case nothing matches in the
earlier branches it will fall back to
default and the variable will be updated
or refreshed and therefore a
combinational circuit element will be
inferred rather than the the rather than
a latch other other thing we can do is
that at the beginning of always block we
assign the value of the signals to a
default value for example we can write
out one is equal to one tick B 0 before
the case statement so the whenever the
always block is triggered out one will
be assign one value right of course it
will be a reassigned later on down the
down the code but it will in all in the
all conditional branches if it the in
sorry in in the conditional branches we
are missing the writing value to the uh
signal out one then this out the value
of out one that we have written at the
top of the always block that will be in
will be will be coming to action and a
combinational circuit element will be
so um
um
to know more into what we have discussed
in this lecture you can refer to this
book and just to summarize what we have
done in this lecture so in this lecture
we have looked into the RTL synthesis so
we saw that RTL synthesis consists of
various tasks for example first the the
parsing of the RTL code is done then the
elaboration is done then we then we
translate the very low construct to the
corresponding logic gates and then add
some optimizations that so the in the
next lecture we will be looking at the
translation of some more verilog
constructs and we we will also look into
ah the optimizations that are RTL
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