hi everyone welcome to vlsi academy this
is a continuation lecture on sanity
checks related to the floor plan which
must be performed to ensure the smooth
execution of your steps related to
physical design so without any delay let
us get started in previous lecture we
broadly covered what sanity is xr so
there were net list related checks there
was sdc related checks and linking
related checks and netlist versus sdc we
had covered why we should be doing the
sanity checks why it is important and we
also covered in detail what netlist
related checks are so uh out of those
netlist related checks there were first
was output should not output should be
should not be tied to the ground so
output should not be
tied to the ground that was the first
check that we saw in the net list
related checks and then second check
that we saw was
input should not be floating so there
should not be any floating input no
floating inputs in the design are
allowed we have seen that in detail why
it is important then we also saw that
there should not be any multi-driven
nets so there should not be any
multi-driven nets in the design that
also we covered in detail then last we
saw was there should not be any
combinational feedback loops so there
should not be any combinational feedback
loops or you can say that no timing
loops should be present in the design
this combinational feedback loop creates
a problem in the sd also and hence it
should be avoided so we have seen all
this and now we will cover in detail
what are sdc related checks let us
assume this is our design and there are
certain ports at the bottom these are
your interface ports and hence in our
sdc related checks first expectation is
your i o delay must be properly defined
if your i o delays are not properly
defined then the interface timing will
not be correct we have covered the
contents of sdc in one of the previous
videos you can go and watch that video
so in that input delay and output delay
are specified using set
underscore input underscore delay this
is for input related and
command for output is set underscore
output underscore delay we have covered
that in detail how do we specify all the
constraints so first expectation is your
io delay should be proper for the proper
interface timing the second sdc related
check is there should not be any
unconstrained endpoints so if you have
any unconstrained endpoints that means
you have a timing path but it is not
constrained if the constraints are
missing that means your sdc is not
correct so unconstrained end point
should be zero we will not be able to
perform timing analysis and optimize
properly if you have unconstrained
endpoints in the design the third check
is related to the flip flop clock pins
so if let us say this is your flip flop
and this is your clock pin so there
should be a clock should be reaching to
that clock pin so we have to check for
that that
no if there is no clock
reaching to that clock pin then timing
optimization will not be correct so no
clock reaching to the
flip flop
clock pin
if that is the case then timing
optimization will not be correct and
setup and hold checks will not be
performed on this particular data pin of
this flip flop so that is not a correct
expectation and hence that could happen
probably because there is no clock
attribute set on this particular clock
pin or even if it is set it might be
propagate not propagated properly or
there could be some other constraint
missing on the clock pin so
because of this that could happen so we
need to check for this also sometimes
what happens is let us say that this
macro is a macro and its pin is this pin here
here
and this pin is getting clock from this
clock source which is giving the clock
as clk a and there is also clock coming
from the different clock source which is
clk b
so what happens is you are getting
multiple clocks on a single clock pin it
could be either macro or it could be on
a standard cell also so both we have to
check for standard cell and macro all
the clock pins there should not be
multiple clocks driving a single clock
pin so it is similar to
no multi driven nets we have seen that
in earlier case of sanity checks so no
multi driven net should be there it is
specifically for clock nets so no multi
driven clock nets there is an
exception that if you have multi-source
cts which is a specific cts that we will
discuss later on in that case you can have
have
multi-driven nets but that is an
exception and a special case we have
seen in previous videos that cell delay
is a function of input transition and
output load we have seen that already
and this transition is of input pin and
output load is on output pin so for for
defining every cell delay it is
important and while defining for a port
also it is needed so if you do not have
any input transition defined for a
particular port that is also a problem
hence while defining a port also so let
us say that this is one port this port
is connected to some cell inside and
then let's say this is an input port so
the connection will be like this inside
now we need to define something which is
connecting outside otherwise this delay
will not be properly modeled and hence
we should define something like set
input transition so let us say that for
all transitions for all the ports if you
want to define as
together so you can define like this set
input underscore transition
so set input transition is the command
that you can use to define some
transition let's say 200 ps and if you
have the values in ns
and inside this you will give all the
input ports so that will be all
underscore inputs
that way you can define so set
underscore input transition is the
command to use used to define the
input transition of the all input ports
similarly for defining proper
constraints for the output ports we must have
have
a defined load on the output ports if
you do not have defined then you can
define like this set underscore load and
let's say some 25 peak of error you want
to define the load as capacitance and
here you will give all underscore outputs
outputs
so this is the command you can use to
define the load and the output ports so
the requirement becomes
that you should have input transition
transition and
and
output load defined
defined on
on
all inputs and output ports on all
input and
output ports this is a requirement to be
defined in the sdc that is all for this
video we will come up with more concepts
in further videos please do like share
Chrome Extension