As chip capabilities increase, the need for faster and more efficient memory integration is driving the evolution of embedded memory technologies beyond traditional SRAM and e-flash, with MRAM and ReRAM emerging as promising next-generation solutions.
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As chips speed up and get more capable,
they must also fetch more data and get
it faster. Most of the time that means
going off chip to some external memory
module. It slows things down and uses
energy. One alternative is to quote
embed some memory right alongside the
logic circuits on the chip. Embedded
memories. For years, two types of
embedded memories dominated. But things
are changing. In today's video, we take
a look at those, plus some of the next
generation memories coming down the pike.
pike.
40 years ago in the 1980s, there were
three big categories of discrete
standalone memory chips. The SRAMMs,
DRAM, and flash EROMs. But as time and
technology demands progressed, these
three changed like high school friends
after graduation. In the 1990s, the
process nodes used to make DAM and flash
memories greatly diverge from each other
as well as the nodes used for making
logic chips.
DRAMs transition from using flat planer
capacitors to vertical ones. And today,
the dominant DRAM nodes use these tall
and skinny capacitors stacked on top of
or below their axis transistors.
And as for the EROMs, they evolved into
the flash memories, NOR and NAND, with
planer NAND evolving yet again into the
lasagnaike 3D NAND. Such vertically
stacked NANDs are some of the most
scalable in the semiconductor world. I
did a video about it a while ago.
Now, as a standalone memory, SRAMM
hasn't had the same success as its two
friends. Unlike DRAMs and EROMs,
however, SRAMMs you can use only
transistors to store bits, which lets us
make it alongside the rest of the chip
on an embedded status without needing
any additional masks. In the late 1980s,
CPU makers started embedding SRAMs onto
their chips as cache to store important
data. It remains very significant and
the single largest embedded memory
market. However, in recent years, SRAMs
have found themselves on the ropes. For
one thing, it's a thick boy. The most
widely used SRAMM cell design uses six
transistors. That is a lot compared to
DRAM, which famously is just one
transistor and one capacitor. And that's
a problem because transistors aren't
getting any smaller nowadays. FABs have
optimized SRAMM to such an extent that
when they brag about their process
nodes, they use SRAMM density to do so.
One of the few hard numbers that TSMC
has publicly announced about their N2
process node is how it can stuff more
SRAMM onto the die.
With CPUs and other systems on chips
getting more advanced, you get
situations where a surprisingly
significant portion of certain chips is
just embedded SRAMM memory. Back in the
2000s, some high performance CPUs had as
much as 70% of their whole dyes being
just SRAMM.
So if SRAM is reaching its density
limits, why not embed something that can
be far denser?
That is why some have turned to embedded
DRAM or ED RAM. It is the same one
transistor, one capacitive structure
just embedded onto the die. With that
skinnier setup, we can stuff five to six
times more ED RAM than SRAMM onto the
same space. ED RAM also uses
significantly less power than SRAMM,
even if you still have to periodically
refresh them. Like with commodity DRAMs,
you use just a third of the power of
SRAMs, not to mention the power saved
from not going off chip. There are also
integration benefits since we are less
likely to get bad connections, bend pins
or other mechanical failure points, etc.
ED RAMs tend to be more reliable. Data
transfers to and from memory have bitter latency.
latency.
But what are the downsides? Memory and
logic process nodes are nowadays very
different. So producing ED RAM adds
maybe four to six masks to the
fabrication process which exposes your
chip to yield risk and higher costs. The
ED RAM market was once quite
considerable used for items like the
Xbox 360. However, its momentum has sort
of petered out in recent years with
fewer industry products being made with
it. However, there seems to be plenty of
compute and memory research done in
academia with it.
Also, like SRAMM, EDRAM is volatile.
Once the power goes out, everything is
forgotten. Ideally, we want something
nonvolatile, something that can hold its
data when the power goes off. So, over
time, vendors have embedded flash
memories onto the chip. Embedded flash
or e-lash. E-lash is a NOR type memory.
With NOR, we string together many
special memory cells, planer transistors
equipped with a floating gate. Electrons
are compelled into that floating gate
through an oxide, raising the
transistors threshold voltage. Nor
arranges these cells in such a way that
we can access them one at a time, random
access, at the cost of less density. Its
younger cousin NAND on the other hand
networks its cells together in strings
of 16 to 128 with each cell source
connected to its neighbor's drain. It
lets us pack cells very closely
together, but also means no random
access. We can only manipulate data in
blocks or pages. That is why we aren't
getting embedded NAND anytime soon.
Programming and erasing e-lash's nor
style networks require high voltages,
something like 9 to 18 volts to compel
the electrons to go in and out of the
floating gate. That's a problem because
standard logic transistors run at about
1 volt. To protect these neighboring
logic transistors from getting fried,
you need deep isolation trenches or some
kind of hardening. NAN requires even
higher voltages than NOR to program and
erase their long strings of cells which
is too high for the die anyway. So E
flash being NOR means it cannot achieve
the same density as NAN has. It also
does not write as fast as SRAMM or DRAM.
It cells also suffer the same endurance
issues as discrete flash memories
breaking down over repeated write
cycles. And same as ED RAM, there is a
fabrication cost. It requires an
additional six to eight mass steps,
which can be more than ED RAM. You take
on more yield risk. Today, e-lash is
most often used to store program code
and data for these small but vital chips
called microcontrollers or MCUs. These
are basically computers on a single
chip, though near as powerful as an
Intel or AMD CPU.
E Flash hit the bill, fit the bill
before these systems because it boots
fast, is power efficient, rewritable,
and can survive the rough conditions
that cars or other industrial devices
often experience. The e-lash automotive
MCU market is often cited as the second
largest overall embedded memory market
after SRAMM, though you can also find
them in edge AI and data center applications.
applications.
E-lash's most serious issue, however, is
scaling. Largely speaking, 28 nanometers
is the end of the road scaling wise for
El. Scaling down E-lash means making
smaller transistors and packing them
closer together. This becomes a serious
issue at 28 nmters, the last planer
transistor node.
There you have all the standard problems
of shrink, loss of control over the
gate, short channel effect, so on. par
for the course and why the logic fabs
switch to 3D finfats. But then there are
the flash memory related issues too. The
flash memory cells are now so physically
small that their floating gates contain
about 100 or so electrons for a
threshold of 1 volt. It takes fewer
electrons leaking to cause significant
degradation. And with the tunnel oxide
layer so thin now that is way more
likely. These scaling problems are why
the NAND makers switch to 3D NAND. You
loosen the floating gates as technical
requirements by resetting their sizes
from 28 nmters to 40 nmters, but then
stack them vertically to achieve massive
storage numbers. 3D NAND is made in a
parallel manner and very cool, some
cases literally, but not a valid
technical pathway for e-lash. Nor is it
economically feasible for the chip
designer to add what can be up to 10
additional mass to produce a wholly
different transistor type onto the chip.
Without a valid successor to e-lash,
OEMs of MCUs and such products might
move back to discrete memories, perhaps
using advanced packaging to put them
together. So fabs and startups have
suggested potential successors, the next
generation memories. And there are a lot
of next generation embedded memories out
there. Let me cut it down to a few such
with serious backing by major foundaries
like TSMC and Samsung. First up are the
magnetoresistive RAMs or M RAMs.
DRAMs and flash memories encode the bit
by storing a charge. The MRAM on the
other hand does it by manipulating
electrical resistance levels. An MRAM
cell is made up of two things. an access
transistor and the magnetic tunnel
junction or MTJ. The latter is where the
magic happens. The MTJ is a tiny
sandwich of ferroagnets and non-magnetic
layers. The simplest MTJ has two
ferroagnets and a very thin insulator
layer in between them. The top
ferroagnet is referred to as the free
layer. The ferroagnet on the bottom is
called the reference or fixed or pinned
layer. Both ferromagnets are usually
made from an iron alloy like cobalt iron
boron and depending on the variant you
may have several pinned layers. As for
the very thin maybe 1 to 2 nm thick
insulator layer that is most often made
of magnesium oxide.
The MTJ works by having an external
current orient to magnetization of the
MTJ's free layer as compared to its
reference or pinned layers. When the
magnetic moments of both ferromagnet
layers are parallel, then the whole MTJ
will have low electrical resistance. So
we can easily run a current through it.
And when the magnetic moments of the two
ferromagnets are not parallel to each
other or antiparallel then the
electrical resistance gets significantly
higher. So in a way it's like twisting a
faucet open or closed. We can map the
two high or low resistance states to a
bit. How is that done? With MRAMS, we
send small currents into the MTJ to try
and discern its resistance state,
comparing it against a middle point
reference level to determine the final value.
value.
The first MRAMs were introduced in the
1980s and are today known as
conventional or fieldswitched MRAMs.
These older memories use magnetic fields
to write to the MTJ, i.e. how we set the
free layer. This magnetic field was
created by running a current through a
wire making this flip an indirect
effect. Basically, that was how we wrote
data to the old fite core memories.
For this mechanism to work, the magnetic
field has to be strong enough to flip
the MTJ's magnetic state. The problem
was that as the MTJ got smaller, it gets
easier for that bit to accidentally flip
due to thermal noise.
Hard disk drives suffer this problem
too. They have something called the
super paramagnetic limit where the
grains in a bit get so small that
thermal energy can flip them. Anyway,
the response by engineers has been to
raise the quotequote flip limit. The
downside of doing that is that we need a
more powerful magnetic field to switch
it when we actually need to do so. When
the MTJ is small, controlling that field
is harder to do. In the 1990s, the field
switch MRAMM was replaced by a new
variant known as spin transfer torque
MRAM, STM RAM. Instead of using a
magnetic field, we send a special
current through the MTJ. Such electrons
flood into the free layer and flip it directly.
directly.
STM RAM is a very promising memory
technology. To start, it's nonvolatile,
so the data stays even after the power
goes off. It does not need to be
continually refreshed. The area savings
are also very significant. It is
basically just the MTJ and an access
transistor. A very DRMish setup. At the
5nmter node, we get like a 43% reduction
as compared to SRAMM.
Despite being a nonvolatile memory, you
can write to it in less than 10 nonds,
which is DAM like speeds and far faster
than flash memories 20 to 100
microsconds. And unlike flash memory,
the cells have very good endurance.
The biggest challenge involves things on
the manufacturing side. The technology
is technically CMOS compatible, but
fabbing the 15 to 20 various metal and
dialectric stacks that make up the MTJ
is challenging. In particular, the
insulating oxide barrier between the
free and pin layers needs to be about 1
to 2 nm wide. Common issues often happen
during the etch or post-tetch process
where oxygen impinges into the insulator
layer to create an effect called birds
beaking. There can also be issues with
the bottom electrode contact which
connects the MTJ to the metal lines.
Roughness in that contact can make the
MTJ's layers rough, too, which causes
the free layer to magnetically
quotequote sync with the reference
layer, thus making it harder to discern
the actual resistance level of the MTJ.
Beyond that, there are scaling issues at
the 3 to 5 nanometer class nodes. The
STM RAM gets so small that we need a
decently strong current to properly
write to it and avoid thermal induced
bit blips. But advanced node transistors
are so small and delicate that such a
current cannot be easily delivered.
The other major e-lash replacement is
resistive RAM or RAM or RAM. I'm going
to say RAM. RAM is another nonvolatile
memory that stores a bit using either a
high or low resistive state. Yes. So a
lot like MRAM. However, the way in which
they go about doing that is very
different and kind of fun. There are a
variety of RERAM cells, but the most
commonly used one is the filamentbased
RAM. It too is a sandwich of a metal
oxide insulator layer between two metal
electrodes. The oxide might be of
elements like hapneium, tantelum or
titanium, but research into more exotic
things like 2D materials is ongoing. The
electrodes can be titanium, platinum or
something else. The rea cell switches
between high and low resistive states by
creating set or destroying reset a small
conductive filament maybe as small as 10
by 10 nmters bridging the two
electrodes. That little filament is
essentially a wire through the naturally
insulating dialectric. We set or reset
the filament by applying a voltage or
current signal to the electrodes. Very
elegant, very simple concept.
The concept reminds me of another memory
called phase change RAM, which uses heat
to switch a ccogenide glass between an
amorphous or crystalline phase. In this
case, RAM does not require the phase
change. Producing embedded RAM requires
fewer mass depths than other embedded
non-volatile memories. It can scale down
to advanced nodes fairly well. It uses
less energy, is nonvolatile, and reads
writes very quickly. On the other hand,
there are some variability and endurance
issues. The set and reset processes
appears to be inherently random, leading
to inconsistent behaviors. Not what you
want in a semiconductor technology. And
I do wonder how many times can we make
and break the filaments before it starts
to exhibit weird behaviors. Broadly
speaking, the technology has commercial
potential, but it also feels like
something that pops his head up every so
often, attempting to ride the latest
significant trend. Between 2005 and
2015, RAM gained serious traction as a
potential successor to 2D NAND until the
rise of 3D NAND closed the door on that.
There were proposals to do stacked RAM,
vertical and horizontal, but those
failed to compete.
A few companies offer this technology
today. There's one called Weebit Bit
Nano from Israel that shows up a lot in
the literature. They've been around for
over 10 years licensing rea to customers
for enduser products. TSMC offers it as
an option for customers too. They have
published a few papers on the technology
though far fewer than what they have on
MRAM. It seems like TSMC is positioning
or TSMC and Samsung are positioning both
technologies as potential successors to
e-lash especially in the automotive MCU
space. There are others like the
affforementioned phase change RAM and
ferro electrics that might have a shot
but I think ST MRAM and RAM are the leaders.
leaders.
Despite both TSMC and Samsung
positioning ST MRAM or RAM e-lash
remains quite resilient. Why Elash is a
tried andrue solution in a space where
reliability matters more than raw
performance. Most MCUs microcontrollers
are still made using trailing edge nodes
like 65 nanmters, though this is
starting to change. And as we laid out
throughout this video, the next
generation contenders are not exactly
free of trade-offs. The semiconductor
industry is pretty conservative and
they're not apt to try new weird stuff
until they have to.
The current major hope for these
embedded nonvolatile memories
technologies is AI since embedded
memories are so close to the logic
literally there's some potential to
evade the vonoyoman bottleneck and that
seems to be the case with STM RAM.
Another option is for doing AI inference
on the device at low power and fast
latency maybe even using neuromorphic
principles to do so. This is more for
ream. In both cases, the technology
seemed to have gotten ahead of the use
case, but we shall see if the enduser
markets can get on board. All right,
everyone. That's it for tonight. Thanks
for watching. Subscribe to the channel.
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